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FEATURES
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LT5554 Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA DESCRIPTION
The LT(R)5554 is a 7-bit digitally controlled programmable gain (PG) amplifier with 16dB gain control range. It consists of a 50 input variable attenuator, followed by a high linearity variable transconductance amplifier. The coarse 4dB input attenuator step is implemented via 2-bits of digital control (PG5, PG6). The fine transconductance amplifier 0.125dB step within 3.875dB gain control range is set via 5-bits digital control (PG0 to PG4). The LT5554 gain control inputs (PGx) and the STROBE input can be directly coupled to TTL or ECL drivers. The seven parallel gain control inputs time skew can be eliminated by using the STROBE input positive transition. The internal output resistor RO = 400 limits the maximum overall gain to 36dB for open outputs. The internal circuitry of open output collectors enables the LT5554 to be unconditionally stable over any loading conditions (including external SAW filters) and provides -80dB reverse isolation at 300MHz. The LT5554 is internally protected during overdrive and has an on-chip power supply regulator. With 0.125dB step resolution and 5ns settling time, the LT5554 is suitable in applications where continuous gain control is required.
1GHz Bandwidth at all Gains 48dBm OIP3 at 200MHz, 2VP-P into 50, ROUT = 100 -88dBc IMD3 at 200MHz, 2VP-P into 50, ROUT = 100 1.4nV/Hz Input-Referred-Noise (RTI) 20dBm Output P1dB at 70MHz, ROUT = 130 2dB to 18dB Gain Range (ROUT = 50) 0.125dB Gain Step Size 30ps Group Delay Variation 5ns Fast Gain Settling Time 5ns Fast Overdrive Recovery -80dB Reverse Isolation
APPLICATIONS
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Differential ADC Driver IF Sampling Receivers VGA IF Power Amplifier 50 Driver Instrumentation
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
OIP3 and SFDR vs Frequency
132 5V VCC 0.1F SFDR (dBm/Hz) IN+ RF INPUT LO IF BPF IF AMPLIFIER DEC IN- 0.1F CDEC 0.1F MODE 130 46 OIP3 (dBm) ROUT = 50 49
-
LT5554 BPF ADC
OIP3
+
7 BITS PGx GAIN CONTROL STROBE
5554 TA01
128 SFDR
43
126
0
50
100 150 FREQUENCY (MHz)
40 200
5554 TA01b
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LT5554 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW GND GND GND GND GND 24 VCC 23 ENB 22 GND 33 21 OUT- 20 OUT+ 19 GND 18 MODE 17 VCC 9 10 11 12 13 14 15 16 PG5 PG6 PG0 STROBE GND GND GND PG1 PG2 PG3 PG4 32 31 30 29 28 27 26 25 GND GND DEC IN+ IN- DEC GND GND 1 2 3 4 5 6 7 8
Supply Voltage VCC..........................................................................6V Pin Voltages and Currents OUT+, OUT- ............................................................7V STROBE, PGx..........................................-0.5V to VCC ENB, MODE.............................................-0.5V to VCC IN+, IN-, DEC ........................................... -0.5V to 4V Operating Ambient Temperature Range LT5554 ............................................... -40C to +85C Junction Temperature ........................................... 125C Storage Temperature Range................. -65C to +150C
UH PACKAGE 32-LEAD (5mm 5mm) PLASTIC QFN TJMAX = 150C, JA = 34C/W, JC = 3C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LT5554IUH#PBF TAPE AND REEL LT5554IUH#TRPBF PART MARKING 5554 PACKAGE DESCRIPTION 32-Lead (5mm x 5mm) Plastic QFN TEMPERATURE RANGE -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LT5554 AC ELECTRICAL CHARACTERISTICS
SYMBOL BW OP1dB GM CMRR S12 PARAMETER Large Signal -3dB Bandwidth Output 1dB Compression Point Amplifier Transconductance at GMAX Common Mode Gain to Single-Ended Output Reverse Isolation Overdrive Recovery Time IIP3 OIP3 IMD3 OIP3 OIP3 HD3 VONOISE NF RTI SFDR Input Third Order Intercept Point Output Third Order Intercept Point for Max-Gain Intermodulation Product for Max-Gain Output Third Order Intercept Point for -3.875dB STEP Output Third Order Intercept Point Third Harmonic Distortion Output Noise Noise Spectral Density Noise Figure Input Referred Noise Spectral Density (RMS) (Note 5) Spurious Free Dynamic Range in 1Hz BW. Maximum Voltage and Power Gain Minimum Voltage and Power Gain Gain Step Size (Note 9) Group Delay Step Accuracy Input Resistance Input Capacitance Output Resistance Output Capacitance CONDITIONS All Gain Settings (Note 7) All Gain Settings, ROUT = 130, 70MHz FIN = 100MHz FIN = 100MHz, Figure 19 FIN = 100MHz FIN = 400MHz 5ns Input Pulse, VOUT within 10% GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz FIN = 100MHz FIN = 200MHz FIN = 100MHz FIN = 200MHz FIN = 100MHz FIN = 200MHz GMAX, F1 = 88MHz, F2 = 112MHz GMAX -3.875dB, F1 = 88MHz, F2 = 112MHz Pout = 10dBm, FIN = 100MHz, GMAX GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz FIN = 112MHz FIN = 100MHz Except For -4dB, -8dB, -12dB Steps For -4dB, -8dB, -12dB Steps FIN = 100MHz FIN = 100MHz, GMAX to GMAX -3.875dB FIN = 100MHz, GMAX -4dB to GMIN FIN = 100MHz FIN = 100MHz FIN = 100MHz 15.3 40.5 38 Dynamic Performance LF - 1000 20 0.15 -6 -86 -78 5 27 30 45 46 -82 -84 44 40 47 44 -62 10.7 7.3 10 10.5 1.34 1.42 128 129 17.6 1.725 0.125 10 43 47 2.8 400 1.9 0.25 0.35 19.7 MHz dBm S dB dB dB ns dBm dBm dBm dBm dBc dBc dBm dBm dBm dBm dBc nV/Hz nV/Hz dB dB nV/Hz nV/Hz dBm/Hz dBm/Hz dB dB dB dB ps pF pF
(ROUT = 50) Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 2.2V, VIH = 2.2V, VIL = 0.6V, maximum gain (Notes 3, 6), (Test circuits shown in Figure 16), unless otherwise noted.
MIN TYP MAX UNIT
Noise/Linearity Performance Two Tones, POUT = 4dBm/Tone (2VP-P into 50), f = 200kHz
Amplifier Voltage Gain and Gain Step GMAX GMIN GSTEP GDERROR RIN CIN RO CO
AMPLIFIER I/O Differential IMPEDANCE
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LT5554 AC ELECTRICAL CHARACTERISTICS
SYMBOL IIP3 OIP3 IMD3 VONOISE NF RTI SFDR GVMAX GPMAX PARAMETER Input Third Order Intercept Point Output Third Order Intercept Point for Max-Gain Intermodulation Product for Max-Gain Output Noise Noise Spectral Density Noise Figure Input Referred Noise Spectral Density (RMS) (Note 5) Spurious Free Dynamic Range in 1Hz BW. Maximum Voltage Gain Maximum Power Gain CONDITIONS GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz FIN = 100MHz FIN = 200MHz FIN = 100MHz FIN = 200MHz GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz GMAX, FIN = 200MHz GMAX -3.875dB, FIN = 200MHz GMAX, FIN = 200MHz FIN = 100MHz FIN = 100MHz
(ROUT = 100) Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 2.2V, VIH = 2.2V, VIL = 0.6V, maximum gain (Notes 3, 8), (Test circuits shown in Figure 16), unless otherwise noted.
MIN TYP 27 27 48 48 -88 -88 21.4 14.5 10 10.5 1.34 1.42 128 23.6 20.6 MAX UNIT dBm dBm dBm dBm dBc dBc nV/Hz nV/Hz dB dB nV/Hz nV/Hz dBm/Hz dB dB Noise/Linearity Performance Two Tones, POUT = 4dBm/Tone (2VP-P into 50), f = 200kHz
AC ELECTRICAL CHARACTERISTICS (Timing Diagram)
SYMBOL TSU THOLD TPW TR TLATENCY TGLITCH AGLITCH PARAMETER Setup Time PGx vs STROBE Hold Time PGx vs STROBE STROBE Pulse Width STROBE Period Latency Time of the Previous Gain State Time Between Previous Stable Gain State to Next Stable State Max Glitch Amplitude Output Settles within 1% Output Settles within 1% VIN = 0 (No Signal or STROBE Transition During Output Signal Zero Crossing) STROBE Transition when Output Power is at Peak + 10dBm Power CONDITIONS PGx and Strobe Timing Characteristics
(ROUT = 50) Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V, maximum gain (Test circuit shown in Figure 16), unless otherwise noted.
MIN TYP 0 1 2 4 4 5 1 3 MAX UNIT ns ns ns ns ns ns mV dB
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LT5554 AC ELECTRICAL CHARACTERISTICS (Timing Diagram)
Timing Diagram
PG0, 1, 2, 3, 4, 5, 6 INPUTS
TSU
THOLD
TPW
STROBE INPUTS
DATA TRANSPARENT
DATA LATCH
TGLITCH TLATENCY
OUT SIGNAL
STATE (i)
STATE (i + 1)
STATE (i + 2)
5554 TD01
DC ELECTRICAL CHARACTERISTICS
SYMBOL VCC VCCO PARAMETER Supply Voltage OUT+, OUT- Output Pin DC Common Mode Voltage Shutdown DC Characteristics, ENB = 0.6V VIN(BIAS) IIL(PG) IIH(PG) IOUT ICC VIL(EN) VIH(EN) IIL(EN) IIH(EN) IIH(EN) DEC, IN+, IN- Bias Voltage PGx, STR Input Current PGx, STR Input Current OUT+, OUT- Current VCC Supply Current ENB Input LOW Voltage ENB Input HIGH Voltage ENB Input Current ENB Input Current ENB Input Current Disable Enable VIN = 0.6V VIN = 3V VIN = 5V VIN = 0.6V VIN = 5V (Note 4) Normal Operating Conditions
Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted.
CONDITIONS MIN 4.75 TYP 5 5 MAX 5.25 6 UNIT V V
2 0 210
2.15
V A A
20 4 5.1 0.6 3 70 220 300 VCC 20
A mA V V A A A
Enable Input DC Characteristics
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LT5554 DC ELECTRICAL CHARACTERISTICS
SYMBOL IIH(DEC) IIL(DEC) VIL(MODE) VOPEN(MODE) VIH(MODE) IIL(MODE) IIH(MODE) VIL VIH IIL(DC) IIH(DC) VIN(AC) VIN(AC)P-P VIN(AC)MAX IIL(AC) IIH(AC) VIN(DEC) VIN(BIAS) RIN GM IODC IOUT(OFFSET) ICC PARAMETER DEC Pin Source Current DEC Pin Sink Current MODE Input LOW Voltage for AC-Couple MODE Input OPEN MODE Input HIGH Voltage MODE Input Current MODE Input Current Input LOW Voltage Input HIGH Voltage Input Current Input Current Input Pulse Range Input Pulse Amplitude Maximum Input Noise Amplitude Input Current Input Current DEC IN+, IN- Bias Voltage INPUT Differential Resistance Amplifier Transconductance OUT+, OUT- Quiescent Current Output Current Mismatch VCC Supply Current VIN = 0.6V VIN = 5V Instantaneous Input Voltage Rise and Fall Time <5ns Rise and Fall Time >80ns No LT5554 Gain Update VIN = 0V VIN = 5V GMAX GMAX GMAX GMIN GMAX VOUT = 5V IN+, IN- Open GMAX, MODE = 0V GMIN, MODE = 0V GMAX, MODE = 5V GMIN, MODE = 5V ICC + 2 * IODC (GMAX) 78 77 75 75 33 -210 310 1.85 1.8 125 0 600 300 100 -155 420 2 2.04 48 50 0.15 47 200 110 109 106 106 200 132 131 127 127 57 -100 530 2.25 2.2 170 2.2 30 220 4.6 DEC External Capacitor Charge/Discharge CURRENT VDEC = 4V VDEC = 1.8V PGx AC-Coupled, STROBE AC-Coupled PGx AC-Coupled, STROBE DC-Coupled PGx DC-Coupled, STROBE DC-Coupled VMODE = 0V VMODE = 5V 27 -70 0 1.7 VCC - 0.4 -42 43 OPEN VCC -31 72 -23 100 0.6 50 -38 70 -14 0.6 2.3 mA mA V V V A A V V A A V mVP-P mVP-P mVP-P A A V V S mA A mA mA mA mA mA
Specifications are at TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, unless otherwise noted. (Note 3) (Test circuit shown in Figure 16), unless otherwise noted.
CONDITIONS MIN TYP MAX UNIT
Mode Input Three-State DC Characteristics
PGx (MODE = VCC) and STROBE (MODE = OPEN or MODE = VCC) INPUTS for DC-Coupled
PGx (MODE = 0V or MODE = OPEN) and STROBE (MODE = 0V) INPUTS for AC-Coupled
Amplifier DC Characteristics
ICC(TOTAL)
Total Supply Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND ground. Note 3: RS = RIN = 50 Input matching is assumed. PIN is the available input power. POUT is the power into ROUT. ROUT = RO || RLOAD is the total output resistance at amplifier open-collectors outputs (used in GV, GP gain calculation). RO = 400 is LT5554 internal output impedance. RLOAD is
load resistance as seen at OUT+, OUT- pins. All dBm figures are with respect to 50. Specifications refer to differential inputs and differential outputs. Note 4: An external power supply equal to VCCO is used for choke inductors or center-tap transformer output interfaces. Whenever OUT+, OUT- pins are biased via resistors, the voltage drop produced by the DCoutput current (IODC = 45mA typical) may require a larger output external power supply. However, care must be taken not to exceed the OUT+, OUT- absolute maximum rating when the LT5554 is disabled.
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LT5554 ELECTRICAL CHARACTERISTICS
Note 5: RTI (Referred-To-Input) stands for the total input-referred noise voltage source. RTI is close to output noise voltage divided by voltage gain (the exact equation is given in Definition of Specification section). The equivalent noise source eN is twice the RTI value. Note 6: The external loading at LT5554 OUT+/OUT- pins is RLOAD = 57. ROUT = RLOAD || RO = 50. Note 7: The IN+, IN-, DEC pins are internally biased. The time-constant of input coupling capacitor sets the low frequency corner (LF) at input. The output coupling capacitors or the transformer sets the low frequency corner (LF) at the output. The LT5554 operates internally down to DC. Note 8: The external loading at OUT+/OUT- pins is RLOAD = 133. ROUT = RLOAD || RO = 100. Note 9: Depending on the actual input matching conditions and frequency of operation, the LT5554 steps involving the input attenuator tap change may show less than 0.125dB change. These steps are GMAX -4dB, GMAX -8dB, GMAX -12dB, and the code is given in the Programmable Gain Table. The LT5554 monotonic operation for 0.125dB step resolution can still be obtained by skipping any such code with a gain error excedding 0.125dB.
(ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted. Gain vs Frequency for 0.5dB Steps, Figure 17
20 18 16 GAIN ERROR (dB) 14 GAIN (dB) 12 10 8 6 4 2 0 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz)
5554 G01
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Gain Error vs Frequency at -40C
0.3
Differential Gain Error vs Frequency at 85C
0.3
0.2 GAIN ERROR (dB) 12dB 0.1 4dB 8dB 0
0.2 12dB 0.1 4dB 8dB 0
-0.1
-0.1
-0.2
50
75
100 125 150 FREQUENCY (MHz)
175
200
5554 G02
-0.2
50
75
100 125 150 FREQUENCY (MHz)
175
200
5554 G03
Differential Gain Error vs Attenuation at 50MHz
0.3 -40C 25C 85C GAIN ERROR (dB) 0.3
Differential Gain Error vs Attenuation at 100MHz
-40C 25C 85C GAIN ERROR (dB) 0.3
Differential Gain Error vs Attenuation at 200MHz
-40C 25C 85C
0.2 GAIN ERROR (dB)
0.2
0.2
0.1
0.1
0.1
0
0
0
-0.1
-0.1
-0.1
-0.2
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G04
-0.2
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G05
-0.2
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G06
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LT5554 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Gain Error vs Attenuation at 50MHz
0.4 -40C 25C 85C GAIN ERROR (dB) 0.4
(ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), unless otherwise noted. Integral Gain Error vs Attenuation at 100MHz
-40C 25C 85C GAIN ERROR (dB) 0.4
Integral Gain Error vs Attenuation at 200MHz
-40C 25C 85C
0.3 GAIN ERROR (dB)
0.3
0.3
0.2
0.2
0.2
0.1
0.1
0.1
0
0
0
-0.1
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G07
-0.1
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G08
-0.1
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G09
Maximum Gain vs Temperature
18.0 24
POUT vs PIN at Maximum Gain
70MHz 140MHz 200MHz 24
POUT vs PIN at GMAX - 3.875dB
70MHz 140MHz 200MHz
17.8
50MHz POUT (dBm) 100MHz 200MHz
16
16
GMAX (dB)
17.6
8
POUT (dBm) -25 -15 -5 PIN (dBm) 5 15
5554 G11
8
17.4
0
0
17.2
-8
-8
17.0 -40
-20
0 20 40 60 TEMPERATURE (C)
80
5554 G10
-16 -35
-16 -35
-25
-15 -5 PIN (dBm)
5
15
5554 G12
(ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50), f = 200kHz, unless otherwise noted. Two-Tone OIP3 vs Frequency at Max Gain, Three Temperatures
49 85C -76
Two-Tone IMD3 vs Frequency at Max Gain, Three Temperatures
32
IIP3 vs Frequency at Max Gain, Three Temperatures
85C
25C 46 OIP3 (dBm) IMD3 (dBc)
-79 IIP3 (dBm) -40C -82 25C
30 25C 28 -40C
-40C 43
-85 85C 40 -88
26
0
50
100 150 FREQUENCY (MHz)
200
5554 G13
0
50
100 150 FREQUENCY (MHz)
200
5554 G14
24
0
50
100 150 FREQUENCY (MHz)
200
5554 G15
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LT5554
(ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50), f = 200kHz, unless otherwise noted. Two-Tone OIP3 vs Frequency for GMAX and Critical Gain Steps
49 -70
TYPICAL PERFORMANCE CHARACTERISTICS
Two-Tone IMD3 vs Frequency for GMAX and Critical Gain Steps
32
IIP3 vs Frequency for GMAX and GMAX -3.875dB
GMAX - 3.875dB 30
GMAX - 12dB 46 OIP3 (dBm) GMAX GMAX - 15.875dB 43 GMAX - 3.875dB -76 IMD3 (dBc) IIP3 (dBm) GMAX - 3.875dB GMAX - 15.875dB
28
GMAX
-82 GMAX - 12dB
GMAX
26
40
50
100 150 FREQUENCY (MHz)
200
5554 G16
-88
24 50 100 150 FREQUENCY (MHz) 200
5554 G17
50
100 150 FREQUENCY (MHz)
200
5554 G18
Two-Tone IMD3 and OIP3 vs Attenuation at 50MHz
-70 OIP3 48 -70
Two-Tone IMD3 and OIP3 vs Attenuation at 70MHz
48 OIP3
-74 IMD3 (dBc)
46 OIP3 (dBm) IMD3 (dBc)
-74
46 OIP3 (dBm)
-78
44
-78 IMD3
44
IMD3 -82 42 -82
42
-86
0
-4
-8 -12 ATTENUATION (dB)
40 -16
5554 G19
-86
0
-4
-8 -12 ATTENUATION (dB)
40 -16
5554 G20
Two-Tone IMD3 and OIP3 vs Attenuation at 100MHz
-70 48 -70
Two-Tone IMD3 and OIP3 vs Attenuation at 140MHz
48 OIP3
-74 IMD3 (dBc)
OIP3
46 OIP3 (dBm) IMD3 (dBc)
-74
46 OIP3 (dBm)
-78
44
-78
44
-82 IMD3 -86
42
-82 IMD3
42
0
-4
-8 -12 ATTENUATION (dB)
40 -16
5554 G21
-86
0
-4
-8 -12 ATTENUATION (dB)
40 -16
5554 G22
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LT5554
(ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50), f = 200kHz, unless otherwise noted. Two-Tone IMD3 and OIP3 vs Attenuation at 200MHz
-70 IMD3 -74 IMD3 (dBc) 46 44 OIP3 (dBm) OIP3 (dBm) OIP3 (dBm) -78 OIP3 -82 42 44 44 50MHz 70MHz 100MHz 140MHz 200MHz 48 47
TYPICAL PERFORMANCE CHARACTERISTICS
Two-Tone OIP3 vs Tone Power at Max-Gain
47
Two-Tone OIP3 vs Tone Power at Min-Gain
41
41 50MHz 70MHz 100MHz 140MHz 200MHz 0 6 9 3 OUTPUT TONE POWER (dBm) 12
5554 G24
-86
0
-4
-8 -12 ATTENUATION (dB)
40 -16
5554 G23
38
38
0
3 6 9 OUTPUT TONE POWER (dBm)
12
5554 G25
Two-Tone OIP3 vs ROUT, for GMAX
50 48
Two-Tone OIP3 vs VCCO, for GMAX
48
Two-Tone OIP3 vs VCCO, for GMAX -3.875dB
45 48 OIP3 (dBm) OIP3 (dBm) 42 OIP3 (dBm) 25MHz 70MHz 140MHz 200MHz 2 3 4 5 OUTPUT COMMON MODE VOLTAGE (V) 6
45
42
46 25MHz 70MHz 140MHz 200MHz 50 75 ROUT () 100
5554 G52
39
39
44
36
36
25MHz 70MHz 140MHz 200MHz 2 3 4 5 OUTPUT COMMON MODE VOLTAGE (V) 6
5554 G28
5554 G30
Harmonic Distortion vs Attenuation, 50MHz, POUT = 10dBm, Figure 17
-70 -75 -80 -85 -90 -95 -100 HD5 -105 35 0 -4 -8 -12 ATTENUATION (dB) -16
5554 G27
OIP3 vs Frequency for GMAX and GMIN, POUT = 10dBm
50
HARMONIC DISTORTION (dBc)
OIP3 (dBm)
HD3
45
GMIN 40 GMAX
50
100 150 FREQUENCY (MHz)
200
5554 G29
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LT5554
(ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16) POUT = 4dBm/tone (2VP-P into 50), f = 200kHz, unless otherwise noted. HD3 vs Frequency for GMAX and GMIN, POUT = 10dBm, Figure 17
-50 -70
TYPICAL PERFORMANCE CHARACTERISTICS
HD5 vs Frequency for GMAX and GMIN, POUT = 10dBm, Figure 17
HARMONIC DISTORTION (dBc)
-56
HARMONIC DISTORTION (dBc)
GMAX
-76
GMAX
-62 GMIN -68
-82
GMIN
-88
-74
-94
-80
50
100 150 FREQUENCY (MHz)
200
5554 G31
-100
50
100 150 FREQUENCY (MHz)
200
5554 G32
(ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted. HD3 and HD5 vs POUT for GMAX, Figure 17
-40 -45 HARMONIC DISTORTION (dBc) -50 -55 -60 -65 -70 -75 -80 7 10 13 OUTPUT POWER (dBm) HD5 0 0 5 5 HD3 HD5 HD3 NF (dB) 10 70MHz 140MHz 20
Noise Figure vs Frequency
20
Single-Ended Output NF vs Frequency, Figure 18
15 GMAX -3.875 NF (dB) GMAX
15
GMAX -3.875 GMAX
10
16
5554 G33
0
200
400 600 FREQUENCY (MHz)
800
5554 G34
0
200
400 600 FREQUENCY (MHz)
800
5554 G35
Noise Figure vs Attenuation, 140MHz
25 6
Input Referred Noise vs Attenuation, 140MHz
12
Output Noise Density vs Attenuation, 140MHz
20 9 15 VONOISE (nV/Hz) 0 -4 -8 -12 ATTENUATION (dB) -16
5554 G37
RTI (nV/Hz)
4
NF (dB)
6
10
2 5
3
0
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G36
0
0
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G38
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11
LT5554
( ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted. Single-Ended Output Current vs Attenuation
98 215 85C 208 CURRENT (mA) 25C 200
TYPICAL PERFORMANCE CHARACTERISTICS
Total ICC Current vs Attenuation
-40C CURRENT (mA) 96 25C 85C 94
193
-40C
92
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G39
185
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G40
ICC Shutdown Current vs VCC, ENB = 0.6V
5 85C -40C CURRENT (mA) 3 25C 2 VIN(BIAS) (V) 2.2
VIN(BIAS) vs Attenuation
4
-40C 2.1 85C
1
25C
0 4.7
4.9
5.1 VCC (V)
5.3
5.5
5554 G41
2.0
0
-4
-8 -12 ATTENUATION (dB)
-16
5554 G42
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LT5554
(ROUT = 50) TA = 25C. VCC = 5V, VCCO = 5V, ENB = 3V, MODE = 5V, STROBE = 3V, VIH = 2.2V, VIL = 0.6V (Test circuit shown in Figure 16), maximum gain, unless otherwise noted. 2dB-Step Response (PG4) 120MHz Signal 8dB-Step Response (PG6) 120MHz Signal 8dB-Step Response (PG6) 120MHz Pulse Signal
TYPICAL PERFORMANCE CHARACTERISTICS
0.1V/DIV
0.1V/DIV
0.2V/DIV
10ns/DIV MODE = HIGH
5554 G46
10ns/DIV MODE = HIGH
5554 G47
5ns/DIV MODE = HIGH
5554 G48
8dB-Step (PG6) 120MHz Pulse Signal for 8dB Overdrive
8dB-Step (PG6) 120MHz Sinusoidal Signal for 2dB Overdrive
8dB-Step (PG6) 120MHz Sinusoidal Signal for 8dB Overdrive
1V/DIV
1V/DIV
1V/DIV
5ns/DIV MODE = HIGH
5554 G49
5ns/DIV MODE = HIGH
5554 G50
10ns/DIV MODE = HIGH
5554 G51
PIN FUNCTIONS
GND (Pins 1, 2, 7, 8, 10, 13, 15, 16, 19, 22, 25, 26, 28, 31): Ground Pins. DEC (Pins 3, 6): Decoupling Pin for the Internal DC Bias Voltage for the Differential Inputs, IN+ and IN-. It is also connected to the `virtual ground' of the input resistive attenuator. Capacitive de-coupling to ground is recommended in order to preserve linearity performance when IN+, IN- inputs are driven with up to 3dB imbalance. IN+ (Pin 4): Positive Signal Input Pin with Internal DC Bias to 2V. IN- (Pin 5): Negative Signal Input Pin with Internal DC Bias to 2V. PG5 (Pin 9): 4dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. PG6 (Pin 11): 8dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by the MODE pin. PG0 (Pin 12): 0.125dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. STROBE (Pin 14): Strobe Pin for the Programmable Gain Control Inputs (PGx). With STROBE in Low-state, the Amplifier Gain is not changed by PGx state changes (latch mode). With STROBE in High-state, the Amplifier Gain is asynchronously set by PGx inputs transitions (transparent-mode). A positive STROBE transition updates the PGx state. Low-state and High-state depends on MODE pin level (Table1). VCC (Pins 17, 24): Power Supply Pins. These pins are internally connected together. MODE (Pin 18): PGx and STROBE Functionality and Level Control Pin. When MODE is higher than VCC - 0.4V, the PGx and STROBE are DC-coupled. When the MODE pin is lower than 0.6V, the PGx and STROBE are AC-coupled.
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LT5554 PIN FUNCTIONS
When the MODE pin is left open, the PGx inputs are ACcouple and the STROBE input is DC-coupled. In DC-coupled mode, the PGx and STROBE inputs levels are 0.6V and 2.2V. In AC-coupled mode, the PGx and STROBE inputs are driven with 0.6VP-P minimum amplitude (with rise and fall time <5ns) regardless the DC voltage level. A positive transition sets a High-state. A negative transition sets a Low-state (for PGx and STROBE inputs). OUT+ (Pin 20): Positive Amplifier Output Pin. A transformer with a center tap tied to VCC or a choke inductor is recommended to conduct the DC quiescent current. OUT- (Pin 21): Negative Amplifier Output Pin. A transformer with a center tap tied to VCC or a choke inductor is recommended to conduct the DC quiescent current. ENB (Pin 23): Enable Pin for Amplifier. When the ENB input voltage is higher than 3V, the amplifier is turned on. When the ENB input voltage is less than or equal to 0.6V, the amplifier is turned off. PG4 (Pin 27): 2dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. PG3 (Pin 29): 1dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. PG2 (Pin 30): 0.5dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. PG1 (Pin 32): 0.25dB Step Amplifier Programmable Gain Control Input Pin. Input levels are controlled by MODE pin. EXPOSED PAD (Pin 33): Ground. This pin must be soldered to the printed circuit board ground plane for good heat dissipation.
BLOCK DIAGRAM
GND (15 PINS) VCC 17 VCC 24 ENB 23
VOLTAGE REGULATOR AND BIAS
ENABLE CONTROL
DEC 3 IN+ 4 IN- 5 DEC 6 ATTENUATOR GAIN LOGIC 4dB STEPS 12dB RANGE PG6 PG5 MODE TRANSCONDUCTANCE GAIN LOGIC 0.125dB STEPS 3.875dB RANGE PG4 PG3 PG2 PG1 PG0 RIN- 25 AMPLIFIER RO 400 OUT+ 20 ATTENUATOR RIN+ 25
OUT- 21
MODE STROBE LOGIC
11
9
18
STROBE
14
27
29
30
32
12
5554 BD
Figure 1. Functional Block Diagram
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LT5554 FUNCTIONAL CHARACTERISTICS
Programmable Gain Table
STATE N 0.125 127 126 125 124 123 122 121 120 119 118 ... 112 111 ... 104 103 ... 96 95 ... 64 63 ... 32 31 ... 8 7 6 5 4 3 2 1 0 L H L H L H L H L L H H L L H H L L L H H H H L L L L H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L -14.875dB -15.000dB -15.125dB -15.250dB -15.375dB -15.500dB -15.625dB -15.750dB -15.875dB GMAX -14.875dB GMAX -15dB GMAX -15.125dB GMAX -15.25dB GMAX -15.375dB GMAX -15.5dB GMAX -15.625dB GMAX -15.75dB GMIN (Min Gain) L H L H L H L H L H H L L L -11.875dB -12.000dB GMAX -11.875dB GMAX -12dB L H L H L H L H L H L H H L -7.875dB -8.00dB GMAX -7.875dB GMAX -8dB L H L H L H L H L H H L H H -3.875dB -4.00dB GMAX -3.875dB GMAX -4dB L H L H L H H L L L H H H H -2.875dB -3.00dB GMAX -2.875dB GMAX -3dB L H L H L H L H H L H H H H -1.875dB -2.00dB GMAX -1.875dB GMAX -2dB H L H L H L H L H L 0.25 H H L L H H L L H H 0.5 H H H H L L L L H H PG0 PG1 PG2 PG3 Step Size in dB 1 H H H H H H H H L L 2 H H H H H H H H H H 4 H H H H H H H H H H 8 H H H H H H H H H H PG4 PG5 PG6 ATTENUATION Step Relative to Max Gain dB (N - 127) * 0.125dB 0.00dB -0.125dB -0.250dB -0.375dB -0.500dB -0.625dB -0.750dB -0.875dB -1.00dB -1.125dB GMAX -1dB GMAX -1.125dB GMAX (Max Gain) GMAX -0.125dB GMAX -0.25dB GMAX -0.375dB GMAX -0.5dB GMAX -0.625dB GMAX -0.75dB GAIN STATE NAME
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LT5554 DEFINITION OF SPECIFICATIONS
Amplifier Impedance and Gain Definitions (Differential) RS RIN CIN RO CO RLOAD CLOAD ROUT Input source resistor. Input matching is assumed: RS = RIN LT5554 input resistance (internal, 50) LT5554 input capacitance (internal) LT5554 output resistance (internal, 400) LT5554 output capacitance (internal) Load resistance as seen by LT5554 output pins Load capacitance as seen by LT5554 output pins Total output resistance at LT5554 open-collectors outputs (used in GV, GP gain calculation): ROUT = RO || RLOAD COUT Total output capacitance at LT5554 output (used in gain calculation): COUT = CLOAD + CO GM LT5554 differential transconductance: GM = IOUT VIN POUT PIN GP GV LT5554 differential voltage gain: V GV = 20 log OUT = 20 log (GM * ROUT ) in dB VIN LT5554 differential power gain: GP = 10log(RIN * GM2 * ROUT) in dB Power available at LT5554 input, RS = RIN = 50 input matching: V 2 IN 2 PIN = 10 log in dBm, (RIN * 1mW ) VIN is peak - value Total power delivered by LT5554 open-collector outputs: V 2 OUT 2 POUT = 10 log in dBm, (ROUT * 1mW ) VOUT is peak - value
INTERNAL OUT+ IOUT = GM * VIN IDC CO 1.9pF RO 400
EXTERNAL
RLOAD
CLOAD VOUT = IOUT * ROUT
ROUT
RO 400
OUT-
5554 F02
RLOAD
ROUT
Figure 2. Output Equivalent Circuit and Impedance Definitions
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LT5554 DEFINITION OF SPECIFICATIONS
Noise Definitions for 50 Matched Input eRS Source resistor RMS noise voltage: eRS2 = 4 * k * T * RS ; for RS = 50, eRS = eN iN vN 0.9nV Hz NF Noise figure in dB according to any of the following equations: eN2 + iN2 * RS2 NF = 10 log 1+ eRS2
2
(
) =

Equivalent short-circuit input RMS noise voltage source Equivalent open-circuit input RMS noise current source Equivalent total input RMS noise voltage source: vN2 = eN2 + iN2 * RS2 (RS = 50) Referred-to-input LT5554 noise voltage: RTI = (eRS + eN + iN * RS ) 2
2 2 2 2
2 1+ V N 1+ RTI 10 log = 10 log 2 e 2 eRS RS 2 Linearity Definitions for 50 Matched Input IMD3[dBc] Third-order intermodulation product (negative value) IIP3 = PIN (per-tone) - IMD3 2
RTI
IIP3[dBm] = vN 2
VONOISE LT5554 output noise voltage: VONOISE =
2 20 eRS 2 RTI + * 10 2 GV
2 SFDR[dBm/Hz] SFDR = * (174 + IIP3 - NF ) 3 OIP3[dBm] OIP3 = POUT - IMD3 = IIP3 + GP 2
APPLICATIONS INFORMATION
Circuit Operation The LT5554 is a high dynamic range programmable-gain amplifier. It consists of the following sections: * An input variable attenuator with 50 input impedance (four 4dB steps, controlled by PG5, PG6 inputs) * A differential programmable transconductance amplifier (32 steps, 0.125dB each controlled by PG0, PG1, PG2, PG3, PG4 inputs) * Programmable logic blocks * Internal bias (voltage regulators) * Enable/disable circuit * Overdrive protection circuit
5554f
Since no internal feedback network is used between amplifier outputs and inputs, the LT5554 is able to offer: * Unconditional stability for I/O reactive loading such as filters (no isolation output resistors required) * High reverse isolation The LT5554 is a class-A transconductance amplifier. An input signal voltage is first converted to an output current via the LT5554 internal GM. And then, the output load (ROUT) converts the output current into an output voltage. ROUT sets the LT5554 gain and output noise floor. However, the SFDR performance is almost independent of ROUT for values of 25 to 100.
17
LT5554 APPLICATIONS INFORMATION
The PGx gain control inputs and STROBE input can be configured to be either DC coupled or AC coupled depending on MODE pin level. The LT5554 gain control inputs can be connected without external components to a wide range of user control interfaces. The LT5554 has internal overdrive protection circuitry. The recovery time from a short duration (less than 5ns) overdrive pulse is 5ns. Input Interface The DC voltage level at the IN+, IN- inputs are internally biased to about 2V when the part is either enabled or disabled. The best linearity performance is achieved when an input imbalance is less than 2dB. Two typical Input connection circuits are shown in Figures 3 and 4. An input source with 50 (5%) is required for best gain error performance.
RSRC/2 25 C1 IN+ 25 VSRC RSRC/2 25 C2 CDEC 0.1F DEC LT5554 25 OUT+
5554 F03
This buffer is also connected to the input resistive attenuator network. The DEC pin is a `virtual ground' and typically connected to an external capacitor CDEC (Figures 3 and 4). When CDEC is used, the LT5554 will have same input attenuation for both differential mode and common mode signals. The DEC pin de-coupling capacitor improves the common mode AC performance even when the differential IN+, IN- inputs are imbalanced by 3dB. The DEC pin can be used as a voltage reference for external circuitry when DC input coupling is desired. Output Interface The output interface must conduct the DC current of about 45mA to the amplifier outputs (OUT+ OUT-). Two interface examples are shown in Figures 5 and 6. A wide band ADC voltage interface is shown in Figure 5 where L1 and L2 are choke inductors. For a narrow band application, a band pass filter can be placed at the LT5554's outputs.
5V C5 MAX GAIN: GV = 24dB GP = 18dB IN+ LT5554 OUT- RO 400 L1 CHOKE INDUCTORS R1 66.5 C3 R2 C6 66.5 L2 VCCO ADC BIAS
OUT-
IN-
DEC
Figure 3. Input Capacitively-Coupled to a Differential Source
IN- IN+ RSRC 50 VSRC ROUT 100 OUT+ RO 400 RLOAD 133 C4
ADC
5554 F05
OUT- 25 LT5554 25 OUT+
5554 F04
RSADC 100
*
*
CDEC 0.1F
DEC
Figure 5. Differential Output Interface
5V MAX GAIN: GV = 24dB GP = 21dB IN+ LT5554 OUT- RO 400 C5 R5 205 VCCO MAX GAIN INTO ZO: GP = 18dB T2 4:1
IN-
Figure 4. Input Transformer-Coupled to Single-Ended Source
Decouple (DEC) Input The DEC pin provides the DC voltage level for differential inputs IN+, IN- via an internal buffer, which is able to fast charge/discharge the LT5554 input coupling capacitors with about 30mA sourcing or sinking current capability.
DEC
* *
R6 205 RO 400 RLOAD 133
*
ZO 50
IN- ROUT 100
OUT+
5554 F06
Figure 6. Single-Ended Matched Output Interface
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LT5554 APPLICATIONS INFORMATION
The differential outputs can also be converted to singleended 50 load using a center-tap transformer interface shown in Figure 6 and Figure 16. The internal 400 differential resistor (RO) sets the output impedance and the maximum voltage gain (GMAX) to 36dB when outputs OUT+, OUT- are open. Figure 7 shows the Voltage and Power Gains as a function of ROUT, which is the total output loading at the open collector amplifier output including the internal resistor RO = 400.
36 VOLTAGE GAIN 30 MAXIMUM GAIN (dB) 24 18 12 6 0 POWER GAIN
Voltage clipping will occur with ROUT >140, in which case the instantaneous voltage at each OUT+ and OUT- outputs is either <2V or >8V. The output OP1dB = 20dBm can be achieved when ROUT = 130. In this case, the LT5554 outputs reach both current and voltage limiting for maximum output power. Gain Control Interface The MODE pin selects the interface to the LT5554 gain control pins. The PGx and STROBE control inputs can be configured to be either DC-coupled (for TTL interface) or AC-coupled (for ECL or low-voltage CMOS interfaces). In addition, the STROBE input can be driven such that the LT5554 gain state is updated asynchronously (PGx latch control in transparent-mode) or controlled by positive STROBE transition (PGx latch control in strobed-mode). There are several options available for coupling type and latch control which are given in the following tables:
10
50
100 ROUT ()
400
1000
5554 F07
Table1. MODE Input Options
MODE (State) LOW OPEN OPEN HIGH HIGH COUPLING TYPE STROBE AC Positive Transition DC >2.2V 0.6 to 2.2V DC >2.2V 0.6 to 2.2V PGx AC AC AC DC DC PGx (Latch Control) Strobe Transparent Strobe Transparent Strobe
Figure 7. Maximum Voltage and Power Gain vs ROUT
The gain vs ROUT relationship is given by the following equations: GV = 20log(GM * ROUT) in dB GP = 10log(RIN * GM2 * ROUT) in dB Where RIN = 50 and GM = 0.15 siemens at GMAX For wide band applications, the amplifier bandwidth can be extended by inductive peaking technique. The inductor in series with the LT5554 outputs (OUT+ OUT-) can have a value up to some tens of nH depending on ROUT value and board capacitance. The current limiting will occur with ROUT <140, in which case the instantaneous signal current at the output exceeds IODC = 45mA.
Table2. MODE Input Levels
MODE (State) LOW OPEN HIGH MODE (Min Level) 0 1.5V VCC - 0.4V MODE (Max Level) 0.6V 2.5V VCC
Alternatively, the MODE pin can be left open (2V internal).
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LT5554 APPLICATIONS INFORMATION
All seven PGx gain control inputs and STROBE input can be configured as DC-coupled or ac-coupled. Accordingly, there are two basic equivalent schematics (shown in Figures 8 and 9) depending on MODE input choice (Table1). Each PGx input circuit shown in Figures 8 and 9 is followed by a transparent latch controlled by the STROBE input level (Table 1). The DC-coupled interface is shown in Figure 8. DC levels for PGx inputs and STROBE input are VIL <0.6V, VIH >2.2V.
VCC R2 1.5k R3 1.5k OUT+ OUT- R1 20k INPUT Q2 Q3 Q1 R4 20k
The AC-coupled interface is shown in Figure 9. The PGx inputs and STROBE input state is decided by a signal transition rather than signal level. A HIGH-state is set by positive transitions. A LOW-state is set by negative transitions. The PGx and STROBE inputs appear as capacitive coupled inputs. The DC voltage (0V to VCC range) presented on any PGx or STROBE input is shifted to the internal 1.4V level by the additional circuit shown in Figure 9. Each PGx and STROBE input has an independent shift circuit such that each input can have a different DC voltage. Each PGx input has a parallel R-C (R1 = 20k, C1 = 2pF) with a 40ns time constant. The STROBE input circuit has R1 = 20k C1 = 3pF and 60ns time constant. An minimum amplitude of 0.6VP-P is required to trip the PGx and STROBE inputs to an appropriate state when the signal period is less than input time constant. The circuit shown in Figure 8 converts the single-ended external signal to an internal differential signal. Consequently, when the input is idle for more than the input time constant, a 0.3VP-P transition will still trigger the gain control state change. All control inputs have 200mV hysteresis to insure stable logic levels when the input noise level is less than 100mVP-P. For transparent latch control, the amplifier gain will be updated directly with any PGx input state changes. If different PGx inputs have an (external) time skew greater than 1ns, then a noticeable amplifier output glitch can occur. The strobe latch control is recommended to avoid this amplifier output glitch. It is not necessary to double buffer the PGx inputs since the LT5554 has good internal isolation from the PGx inputs to the amplifier output to any type of external gain control circuit without external components. If LT5554 is powered up or enabled in latch mode, the LT5554 gain initial gain is indeterminate. If the minimum gain state is desired at power up, it is recommended to set the transparent-mode with all PGx inputs low.
C1 2pF DC-COUPLED
I1 200A
IDC
V1 1.4V
5554 F08
Figure 8. DC-Coupled PGx and STROBE Equivalent Inputs (Simplified Schematic)
VCC R2 1.5k I3 R1 20k INPUT Q2 Q3 IDC R3 1.5k OUT+ OUT- Q1 R4 20k
C1 2pF AC-COUPLED I2 IDC I1 200A V1 1.4V
5554 F09
IDC
Figure 9. AC-Coupled PGx and STROBE Equivalent Inputs (Simplified Schematic)
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LT5554 APPLICATIONS INFORMATION
Gain Step Accuracy LT5554 internal input signal coupling to the transconductance amplifier inputs across the 4dB step attenuator increases with frequency. The gain step error is higher when the LT5554 gain update changes the input attenuator tap (PG5, PG6 transitions) and this error is frequency dependent. Gain error is `compressive', effectively reducing LT5554 gain range. Therefore, it is possible to skip one gain code whenever PG5, PG6 transitions are involved in order to preserve high-frequency monotonic behavior for 0.125dB steps. Linearity and Noise Performance Throughout the Gain Range The LT5554's Noise and Linearity performance across the 16dB gain range at 100MHz with ROUT = 100 and RSADC = 50 is shown in Figures 10 through 13.
12 VONOISE RTI AND VONOISE (nV/Hz) 9
24
44
136
18 IIP3 (dBc)
39 SFDR NF (dB)
132 SFDR (dBm/Hz)
6 NF 3 RTI 0
12
34
128
6
29
IIP3
124
0
-4
-8 -12 ATTENUATION (dB)
0 -16
5554 F10
24 0 -4 -8 -12 ATTENUATION (dB)
120 -16
5554 F11
Figure 10. Noise, 140MHz, ROUT = 50
-70 48
Figure 11. Noise, 140MHz, ROUT = 50
-70 OIP3 48
-74 IMD3 (dBc)
OIP3
46 OIP3 (dBm) IMD3 (dBc)
-74
46 OIP3 (dBm)
-78
44
-78
44
-82 IMD3 -86 0 -4 -8 -12 ATTENUATION (dB)
42
-82 IMD3
42
40 -16
5554 F12
-86
0
-4
-8 -12 ATTENUATION (dB)
40 -16
5554 F12
Figure 12. Linearity, 70MHz, ROUT = 50, 4dBm/Tone
Figure 13. Linearity, 140MHz, ROUT = 50, 4dBm/Tone
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LT5554 APPLICATIONS INFORMATION
The LT5554 Noise and Linearity performance throughout the 16dB gain range has an obvious discontinuity at every 4dB gain step. The noise figure is fairly constant from 0dB (Maximum Gain) to -3.875dB attenuation when the gain is decreased by lowering the amplifier transconductance. And then, the NF increases by 4dB when the input attenuator is switched to -4dB attenuation while the amplifier gain is switched back to maximum transconductance. This pattern repeats for each 4dB gain step change. SECOND ORDER HARMONIC DISTORTION Balanced differential inputs and outputs are important for achieving excellent second order harmonic distortion (HD2) of the LT5554. When configured in single-ended input and output interfaces, therefore, the single-ended to differential conversion at the input and differential to single-ended conversion at the output will have significant impact on the HD2 performance. Figure 14, for example, shows the desirable singe-ended input and output configuration using external transformers for the single-ended to differential conversion and differential to single-ended conversion. To assure a good HD2 performance, R5 and R6 should also be matched to better
C4 0.1F T1 1:1 IN+ VCC = 5V R5 68.1 OUT- LT5554 RO 400 OUT+ C3 0.1F R6 68.1 VCCO = 5V
than 1% or use these two resistors with 1% component tolerance. In this case, the HD2 can be as good as -80dBc when the output power is 10dBm at 140MHz. When the single-ended input is not converted into well balanced inputs to LT5554, the HD2 performance will be degraded. For instance, when the T1 transformer is improperly rotated by 90 degrees as shown in Figure 15, the imbalance of the differential input signals will result in 14dB degradation in HD2. It is also important to split the differential R7 resistor into two single-ended R5 and R6 resistors at the outputs to reduce the imbalance of the T2 transformer. If not, 3dB degradation in HD2 performance can also be observed.
C4 0.1F IN+ T1 1:1 C1 47nF DEC 50 RO 400 OUT+ VCC = 5V VCCO = 5V
OUT- LT5554 R7 134 C3 0.1F
T2 TC2-1T
ETC1-1-13
*
* *
*
*
IN- C2 47nF C5 1F
5554 F15
Figure 15. Not Recommended Single-Ended Input and Output Configuration, HD2 = -63dBc at 10dBm, 140MHz
*
*
DEC 50
T2 TC2-1T
* *
*
ETC1-1-13
IN- C5 1F
The HD2 performance can be further improved by mounting a capacitor from IN+ to ground (a few pF) and a capacitor from OUT- to ground. For narrow band applications, these capacitors cancels to some degree the T1 and T2 imbalance as shown in Figure 15.
5554 F14
For optimum HD2 performance, fully differential input and output interfaces to the LT5554 part are recommended.
Figure 14. Recommended Single-Ended Input and Output Configuration, HD2 = -80dBc at 10dBm, 140MHz
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LT5554 APPLICATIONS INFORMATION
Layout Considerations Attention must be paid to the printed circuit board layout to avoid output pin to input pin signal coupling (external feedback). The evaluation board layout is a good example. The exposed backside pad on the LT5554 package must be soldered to PCB ground plane for thermal considerations. Characterization Test Circuits The LT5554's typical performance data are on the test circuits shown in Figures 16, 17 and 18 which are simplified schematics of the evaluation board schematic from Figure 21. The transformer board from Figure 16 was used for characterization as a function of ROUT. For each ROUT option, The T2 transformer model and the matching resistors R5, R6 values are given in Table 3. The T2 transformer total matching resistance is RMATCH = RO || (R5 + R6) (part LT5554 internal, and part on board R5 and R6).
Table 3. Transformer Board ROUT Options
ROUT () T2 (Mini-Circuits) NLOAD Ratio RLOAD () R5, R6 () GP_BOARD (dB) IL(T2) at 200MHz (dB) 50 TC2-1T 2 57.1 68.1 13.2 -0.6 75 TC3-1T 3 92.3 124 16 -0.65 100 TC4-1W 4 133.3 205 17.2 -1
J5, 40 PINS SMT-TB 1, 3, 5, 7 9 11 ENB 13 15 17 19 21 23 25 27 29 VPG R26 10k PG6 C19 4.7F 31 MODE 33, 35, 37, 38 VCCO 2, 4, ...40 VCC VDEC PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE R20 10k C4 0.1F C8 0.1F PG0 R21 10k PG1 R22 10k PG2 R23 10k PG3 R5 68.1 R24 10k PG4 R25 10k PG5 C3 0.1F
J1 50
T1 1:1
IN+
*
*
IN-
RIN 50 RO 400
OUT- LT5554
OUTPUT MATCHING C18 0.1F
* *
*
J3 50
OUT+ RO 400 RLOAD 57.1 R6 68.1 C9 0.1F
ETC1-1-13 MACOM
C5 1F ROUT = 50
T2 TC2-1T 2:1
VCC = 5V VCCO = 5V
5554 F16
Figure 16. Single-Ended Transformer Test Board (Simplified Schematic)
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LT5554 APPLICATIONS INFORMATION
The LT5554 output power POUT was obtained by adding 3dB for matching-loss and the transformer loss IL(T2) in Table 3 to the board output power at J3 connector. The transformer insertion loss (frequency and temperature dependent) has been included in characterization. The output power matching is required when LT5554 drives a 50 transmission line as shown on the evaluation board. When LT5554 drives local (on-board) loads such that an ADC part, output power matching is not required and OIP3 is defined based on POUT, total power at LT5554 open collector outputs. Figure 17 shows the evaluation board for wide-band characterization at ROUT = 50, where the insertion loss of the output balun is about -1dB at 1GHz. Several ROUT options are given in Table 4 as well as the output padding insertion-loss and required VCCO for 5V on LT5554 outputs. The LT5554 output power at open collector outputs is: POUT = PWR(J3) + IL(T2) + 3dB + ILPAD
J5, 40 PINS SMT-TB 1, 3, 5, 7 9 11 ENB 13 15 17 19 21 23 25 27 29 VPG R26 10k PG6 C9 0.1F C18 0.1F C19 4.7F T2 1:1 50 MATCHING J3 50 31 MODE 33, 35, 37, 38 VCCO 2, 4, ...40 VCC VDEC PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE R20 10k PG0 C4 0.1F C8 0.1F IN+ R21 10k PG1 R22 10k PG2 R23 10k PG3 R24 10k PG4 R25 10k PG5 C3 0.1F OUT- LT5554 R3 15.4 R5 28 R6 28 R4 15.4 RLOAD RO 400 57.1
Table 4. Balun Board ROUT Options
ROUT () R3, R4 () R5, R6 () ILPAD VCCO (V) 25 0 28.7 0 6.29 36 6.49 28.7 1.88 6.57 50 15.4 28 3.66 6.96 71 30.1 28 5.76 7.61 100 53.6 28 8.08 8.66
The differential-output board from Figure 18 was used for ROUT = 50 wide-band characterization of the LT5554 single-ended outputs. Both Figure 17 and Figure 18 boards VCCO was shifted up with the voltage drop on R5, R6 produced by 45mA output DC current such that OUT+, OUT- DC bias voltage is still 5V. The LT5554 part should be always enabled when VCCO >6V. If disabled, the VCCO will be applied at OUT+, OUT- exceeding the absolute maximum 6V limit with possible LT5554 failure.
J1 50
T1 1:1
*
*
IN-
RIN 50 RO 400
*
*
OUT+
ETC1-1-13 MACOM
C5 1F ROUT = 50
ETC1-1-13
5554 F17
VCC = 5V VCCO = 7V
Figure 17. Single Ended Test Board (Simplified Schematic)
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LT5554 APPLICATIONS INFORMATION
J5, 40 PINS SMT-TB 1, 3, 5, 7 9 11 ENB 13 15 17 19 21 23 25 27 29 VPG R26 10k PG6 C9 0.1F C18 0.1F C19 4.7F J3 50 100 MATCHING C10 47nF 31 MODE 33, 35, 37, 38 VCCO 2, 4, ...40 VCC VDEC PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE R20 10k PG0 C4 0.1F C8 0.1F IN+ R21 10k PG1 R22 10k PG2 R23 10k PG3 R24 10k PG4 R25 10k PG5 C3 0.1F OUT- LT5554 R5 66.5 R6 66.5
J1 50
T1 1:1
*
*
IN-
RIN 50 RO 400
OUT+ RO 400 RLOAD 57
ETC1-1-13 MACOM
C5 1F ROUT = 50
J33 50 C12 47nF
5554 F18
VCC = 5V VCCO = 8V ENB = 5V
Figure 18. Wideband Differential Output Test Board (Simplified Schematic)
Common mode characterization for the LT5554 was performed with input circuit shown in Figure 19.
C1 47nF J1 50 25 25 25 CDEC 47nF DEC IN- IN+ OUT-
-
LT5554
+
OUT+
5554 F19
source is applied at J6 connector and 50 terminated by R16 and R33 resistors. C66 decouple R33 to ground while C16 provides DC-decoupling between referenced to ground pulse source and the PG6 DC-voltage. A supply connected to PG6 turret will set the PG6 DC-voltage in 0V to 5V range. All other (untested) PGx DC-voltage can be independently be applied at VPG turret decoupled by C88. Strobe-mode operation is tested with a pulse source applied at J7 connector as shown in Figure 20. Applying similar modifications around J2 and J4 connectors shown in Figure 21, other PGx inputs can be evaluated. As described in Table 1 and Table 2, the MODE pin will select the desired state.
Figure 19. Common Mode Input Interface
Timing characterization and AC-coupled gain control inputs are tested on evaluation board. The required circuit modifications are shown in the Figure 20 simplified schematic and detailed below for PG6 (8dB step). The PG6 pulse
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25
LT5554 APPLICATIONS INFORMATION
R21 10k PG1 PG2 R28 0 32 R8 0 VDEC 1 2 3 4 5 6 7 8 C5 1F GND GND DEC IN+ IN
-
R22 10k
R23 10k
R24 10k
C88 47nF PG4 PG3
VPG
R29 0 31 30 29
R30 0 28
R31 0 27 PG4 26 25 VCC ENB GND OUT - 24 23 22 21 20 19 18 17
C4 0.1F
PG1 GND PG2 PG3 GND
GND GND VCC ENABLE
LT5554
OUT
+
DEC GND GND 9 10 11 12 13 14 15
GND MODE VCC 16
PG5 GND PG6 PG0 GND STROBE GND GND
C8 0.1F
MODE C6 47nF
R16 100 J6
C16 47nF PG5
R32 0 PG6 C27 47nF
R33 100
R27 R34 0 100 PG0
C17 47nF
R17 100 J7
C28 47nF R26 10k R20 10k STROBE
5554 F20
R25 10k
Figure 20. Timing Test for PG6 and STROBE (Simplified Schematic)
Evaluation Board Figure 21 shows the schematic of the LT5554 evaluation board. Transformer T2 is TC2-1T and resistor R5 + R6 = 134 (ROUT = 50 GP(J3) = 13.2dB). The silkscreen and layout are shown in Figures 22 through Figure 27. The board control J5 edge connector (40PINS SMT-TB) allows easy access to LT5554 component pins. Alternatively or combined with J5, 14 test points (turrets) for signals and two for GND are also available. The board is powered with a single supply in 4.75V to 5.25V at VCC and VCCO (either J5 connector or turrets). Connecting the ENABLE pin to
VCC supply enables the LT5554 part. PGx gain control and STROBE inputs will have TTL levels (DC-coupled) when MODE = 5V (same power supply). To set LT5554 for maximum gain (GMAX) in transparent-mode, all seven PGx and STROBE can be connected to 5V supply. Alternatively, a 2.2V power supply at VPG pin and STROBE turret will set same GMAX state. J1 (input) and J3 (output) are the default board signal ports for evaluation with 50 single ended test system. For differential evaluation, the board J11 and J33 connectors must be reconfigured.
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26
LT5554 APPLICATIONS INFORMATION
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J5, 40 PINS SMT-TB VCC 1 VCC 3 VCC 5 VCC VDEC ENB 7 9 11 PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE VPG MODE 13 15 17 19 21 23 25 27 29 31 VCCO VCCO VCCO VCCO 33 35 37 39
VDEC ENB VCC
PG0 PG1 PG2 PG3 PG4 PG5 PG6 STROBE VPG MODE VCCO PG1 PG4 R31 0 PG2 PG3 R29 0 R30 0 C14 47nF VPG R20 10k NOT MOUNTED J4 C21 0.1F PG0 C22 0.1F R21 10k PG1 C23 0.1F R22 10k PG2 C24 0.1F R23 10k PG3 C25 0.1F R24 10k PG4 C26 0.1F R25 10k PG5 C27 0.1F R26 10k PG6
NOT MOUNTED J2
C11 47nF
R28 0
NOT MOUNTED NOT MOUNTED R12 C12 47nF
NOT MOUNTED C13 47nF NOT MOUNTED R14
C21 THROUGH C27 ARE NOT MOUNTED
NOT MOUNTED 32 R8 0 1 2 3 GND GND DEC IN+ IN- DEC GND GND 9 NOT MOUNTED R33 0 R27 0 R34 0 10 11 12 13 14 LT5554 31 30 29 28 27
NOT MOUNTED 26 25
VCCO C4 24 23 22 21 20 19 18 17 C8 0.1F MODE C6 47nF R4 0 R6 681 C9 0.1F C18 0.1F MINICIRCUITS R2 0 NOT MOUNTED R7 NC VCC ENABLE R3 0 C3 0.1F R5 68.1 T2 - TC2-1T OUT 2:1 C19 4.7F
PG1 GND PG2 PG3 GND
PG4
GND GND VCC ENB GND OUT- OUT+ GND MODE VCC 15 16
VDEC J1 IN+ T1 1:1
J3
*
IN-
*
4 5 6
* *
*
OUT+
J11
ETC1-1-13 MACOM R1 0
7 8 C5 1F
J33
NOT MOUNTED
PG5 GND PG6 PG0 GND STROBE GND GND
NOT MOUNTED R16
NOT MOUNTED
5554 F21
R17 NOT MOUNTED NOT MOUNTED J7
C16 47nF NOT MOUNTED R32 0 PG5
C17 47nF
NOT MOUNTED J6
PG6 PG0
STROBE
C15 47nF
Figure 21. Evaluation Circuit Schematic
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27
LT5554 APPLICATIONS INFORMATION
Figure 22. Top Side
Figure 23. Inner Layer 2 GND
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28
LT5554 APPLICATIONS INFORMATION
Figure 24. Inner Layer 3 Power
Figure 25. Bottom Side
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29
LT5554 APPLICATIONS INFORMATION
Figure 26. Silkscreen Top
Figure 27. Silkscreen Bottom
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30
LT5554 PACKAGE DESCRIPTION
UH Package 32-Lead Plastic QFN (5mm x 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 0.05
5.50 0.05 4.10 0.05 3.50 REF (4 SIDES) 3.45 0.05
3.45 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 3.45 0.10 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER
3.50 REF (4-SIDES)
3.45 0.10
(UH32) QFN 0406 REV D
0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LT5554 RELATED PARTS
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COMMENTS
RF Power Detectors LTC(R)5505 LTC5507 LTC5508 LTC5509 LTC5530 LTC5531 LTC5532 LT5534 LTC5536 LT5537 LT5538 LT5570 RF Power Detectors with >40dB Dynamic Range 100kHz to 1000MHz RF Power Detector 300MHz to 7GHz RF Power Detector 300MHz to 3GHz RF Power Detector 300MHz to 7GHz Precision RF Power Detector 300MHz to 7GHz Precision RF Power Detector 300MHz to 7GHz Precision RF Power Detector 50MHz to 3GHz Log RF Power Detector with 60dB Dynamic Range Precision 600Mhz to 7GHz RF Power Detector with Fast Comparator Output Wide Dynamic Range Log RF/IF Detector 3.8GHz Wide Dynamic Range Log Detector 2.7GHz RMS Power Detector
32 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0708 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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